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Category: System On Chip IP Cores (74)

Assembler With VHDL User-defined Commands (AVUC)

Assembler With VHDL User-defined Commands (AVUC)

Here is proposed a method to implement short structured programs inside an FPGA. The novelty of the proposed method resides in that the commands…

License : LGPL
Language : VHDL
EPC RFID Transponder

EPC RFID Transponder

n/a

License : LGPL
Language : VHDL
GECKO4 SoC Co-design Environment

GECKO4 SoC Co-design Environment

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : Others
Language : VHDL
Generic AHB Matrix

Generic AHB Matrix

Generic AHB matrix. It is a multi-master, multi-slave non-blocking AHB matrix with round-robin arbitration. Builds Verilog AHB matrices according…

License : LGPL
Language : Verilog
Generic AXI Interconnect Fabric

Generic AXI Interconnect Fabric

Generic AXI interconnect fabric. It is a multi-master, multi-slave non-blocking AXI fabric with round-robin arbitration. Builds Verilog AXI…

License : LGPL
Language : Verilog
Generic AXI To AHB Bridge

Generic AXI To AHB Bridge

Generic AXI to AHB bridge. Built according to input parameters: AXI command depth, data bits, etc. Supports error on illegal AHB bursts and AHB…

License : LGPL
Language : Verilog
Generic AXI To APB Bridge

Generic AXI To APB Bridge

Generic AXI to APB bridge. Builds design according to required number of slaves, address decoding, AXI command depth, etc. Supports decode error,…

License : LGPL
Language : Verilog
PSS (Programmable Supervisor For Systems-on-Chip)

PSS (Programmable Supervisor For Systems-on-Chip)

PSS (Programmable Supervisor for Systems-on-chip) is a soft IP core that targets to provide the basic means for conducting service operations…

License : BSD
Language : Verilog & VHDL
Or1k SoC Altera Embedded Dev Kit for OpenRISC 1200 Implementation

Or1k SoC Altera Embedded Dev Kit for OpenRISC 1200 Implementation

This project is to implement a SoC of using OpenRISC 1200 and many open source IP cores from opencores.org on Nios II Embedded Evaluation Kit…

License : LGPL
Language : Verilog
Asynchronous Spatial Division Multiplexing Router for NoCs

Asynchronous Spatial Division Multiplexing Router for NoCs

Asynchronous Spatial Division Multiplexing Router for On-Chip Networks Version: 0.2 On-chip networks or networks-on-chip (NoCs) are the on-chip…

License : LGPL
Language : Verilog
ECO32 32-bit RISC Microprocessor SoC

ECO32 32-bit RISC Microprocessor SoC

The ECO32 system is a microprocessor system-on-chip, consisting of a 32-bit CPU and several controllers for peripheral devices (keyboard, character…

License : BSD
Language : Verilog
GECKO3 SoC General Purpose Co-design Environment

GECKO3 SoC General Purpose Co-design Environment

The GECKO system is a general purpose hardware/software co-design environment for real-time information processing and/or system-on-chip (SoC)…

License : Others
Language : VHDL
AHB to Wishbone Protocol Bridge

AHB to Wishbone Protocol Bridge

AHB Protocol to Wishbone Protocol Bridge. Features - AHB 2.0 compliant - Wishbone B.3 compliant - AHB Burst NOT SUPPORTED - Fully synthesisable -…

Language : Verilog
32/64 bits AHB Master DMA Core

32/64 bits AHB Master DMA Core

Single channel 32 or 64 bit AHB master DMA core. Supports simultaneous read and write, command lists, peripheral control, timeouts and endianess…

License : LGPL
Language : Verilog
AMBAtm Specification Compliant AHB System Generator

AMBAtm Specification Compliant AHB System Generator

The intention is to provide an easy way to configure, create and simulate a "complete" AHB system. The main block is the "AHB…

License : LGPL
Language : VHDL
Minimal OpenRISC System on Chip Implementation

Minimal OpenRISC System on Chip Implementation

The Minimal OpenRISC System on Chip is a system on chip (SoC) implementation with standard IP cores available at OpenCores. This implementation…

License : LGPL
Language : Verilog
aoOCS - Wishbone Amiga OCS SoC Implementation

aoOCS - Wishbone Amiga OCS SoC Implementation

The OpenCores aoOCS SoC is a Wishbone compatible implementation of most of the Amiga Original Chip Set (OCS) and computer functionality. aoOCS is…

License : BSD
Language : Verilog
Open Source ARM VHDL Model

Open Source ARM VHDL Model

A open source ARM vhdl model. The annotated vhdl source can be browsed here: http://cfw.sourceforge.net/build_html/vhdl/index.htm Features Note:…

Language : VHDL
32/64 bits AXI master DMA Core

32/64 bits AXI master DMA Core

Single channel 32 or 64 bit AXI master DMA core. Supports simultaneous read and write, outstanding AXI commands, command lists, peripheral control,…

License : LGPL
Language : Verilog
AXI4 Transactor and Bus Functional Model Implementation in VHDL

AXI4 Transactor and Bus Functional Model Implementation in VHDL

This project implements the AXI4 transaction-level model (TLM) and bus functional model (BFM) in VHDL. Currently, only the AXI4-Stream Master…

License : LGPL
Language : VHDL