Asynchronous Spatial Division Multiplexing Router for NoCs

Asynchronous Spatial Division Multiplexing Router for NoCs


Category: System on Chip

Created: May 09, 2011

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Stable

Additional info: ASIC proven, Design done, Specification done

WishBone compliant: No

WishBone version: n/a

License: LGPL


Asynchronous Spatial Division Multiplexing Router for On-Chip Networks

Version: 0.2

On-chip networks or networks-on-chip (NoCs) are the on-chip communication fabric for
current and future multiprocessor SoCs (MPSoCs) and chip multiprocessors (CMPs).
Compared with synchronous NoCs, asynchronous NoCs have following benefits:
* Tolerance to all kinds of delay variations caused by process, power and temperature
* Low transmission latency.
* Zero dynamic power when idle.
* Unified sync/async interface and easy clock domain integration.

Most NoCs use the wormhole flow control method. Many complex flow control methods are
built upon the wormhole method, such as virtual channel (VC), TDMA, and SDM. VC is the
most utilized flow control in both sync and async NoCs. However, it is found VC
compromises the throughput performance of asynchronous NoCs. This project provides a new
asynchronous router structure which use SDM rather than VC. It has been shown that SDM
achieve better throughput than VC in the same router configuration.

This project provide a reconfigurable asynchronous SDM router which can be configured
into a basic wormhole router or an SDM router with multiple virtual circuits in every

* 5-port router for mesh network (0 south, 1 west, 2 north, 3 east, 4 local)
* The dimension order routing (XY routing)
* Available flow control methods: wormhole, SDM, VC
* Reconfigurable number of virtual circuits, buffer size, data width
* Fully synthesizable router implementation
* SystemC testbench provided

* Routers are written in synthesizable SystemVerilog
* Test benches are provided by SystemC

Software requirements:
* The open source Nangate 45nm cell library
* Synopsys Design Compiler (Synthesis)
* Cadence IUS -- NC Simulator (for SystemC/Verilog co-simulation)