Assembler With VHDL User-defined Commands (AVUC)

Assembler With VHDL User-defined Commands (AVUC)


Category: System on Chip

Created: July 14, 2009

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Beta

Additional info: Design done, Specification done

WishBone compliant: No

WishBone version: n/a

License: LGPL


Here is proposed a method to implement short structured programs inside an FPGA. The novelty of the proposed method resides in that the commands that constitute the executable program are defined directly by the user in VDHL code. Applying this method, the resolution of a problem can be partitioned in two: on the one hand, the complex hardware functions can be implemented by the VHDL definitions, while, on the other hand, the higher level take of decisions, loops, iterations and conditional branching or testing can be assumed by the executable program.
The user has to follow two steps: first, to define, using VHDL, the commands that form the language, and second, to write the program using the commands that have been defined before.

Future improvements

Implementation of predefined commands call and return, making possible the use of subroutines. This should come with the creation of a simple stack.