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LinkedinFully Synthesizable Tensilica PIF2WB IP Core Bridge
Details
Category: System on Chip
Created: Aug 04, 2007
Updated: Jan 27, 2020
Language: VHDL
Other project properties
Development Status: Beta
Additional info: Design done, Specification done
WishBone compliant: Yes
WishBone version: n/a
License: n/a
Description
This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.
Features
- PIF master support
- Wishbone slave support
- Burst transfers support
- VHDL RTL
- Fully synthesisable
Status
- RTL: Complete
- Document: Complete
