SimpCon - a Simple and Efficient SoC on-chip Interconnect

SimpCon - a Simple and Efficient SoC on-chip Interconnect


Category: System on Chip

Created: November 28, 2005

Updated: January 27, 2020

Other project properties

Development Status: Stable

Additional info: FPGA proven

WishBone compliant: No

WishBone version: n/a

License: LGPL


SimpCon is a specification for a simple and efficient system-on-chip (SoC) interconnect. SimpCon provides single cycle commands and provisions for pipelining of read and write connections. SimpCon is public domain and freely available.

Translation to and from Wishbone, the opencores standard interface, are provided.

Documentation is in the CVS at

A paper published at the Austrochip on SimpCon is available from:


- Synchronous interface
- Master/Slave connection
- Piplined transactions
- Low resource usage
- Simple to implement


- First draft document written
- Master implemented for JOP in Cyclone and Spartan-3
- Slave for SRAM access (read pipeline level 2)
- JOP IO devices connected as SimpCon slaves
- Wishbone/SimpCon bridge available