MIPS I 512 MBit DDR Ram layer 2 SoC

MIPS I 512 MBit DDR Ram layer 2 SoC

Details

Category: System on Chip

Created: May 01, 2012

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Beta

Additional info: Design done, FPGA proven, Specification done

WishBone compliant: No

WishBone version: n/a

License: GPL

Description

The following components are implemented and tested on silicon:

  • MIPS I(tm) CPU @ 50MHz
  • Intel StratFlash
  • PS/2 Keyboard
  • 100x37 8-Color Text-VGA
  • 19200/8N1 RS-232 Receiver/Transmitter
  • 512 MBit DDR Ram

 

General Notice

Every component consists of an implementation and an interface file i*.vhd where I credited (hopefully) all resources.

Legal Notice

Copyright (C)2012 Mathias Hörtnagl
This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version.
This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along with this program. If not, see http://www.gnu.org/licenses/