WISHBONE Interconnect Matrix IP Core
Details
Category: System on Chip
Created: October 23, 2001
Updated: January 27, 2020
Language: Verilog
Other project properties
Development Status: Stable
WishBone compliant: Yes
WishBone version: n/a
License: n/a
Description
This is a WISHBONE Interconnect Matrix IP core.It can interconnect up to 8 Masters and 16 Slaves
Some of the main features are:
- Up to 8 Masters
- Up to 16 Slaves
- 1, 2 or 4 priority levels
- Fully configurable
IMAGE: conmax.jpg
FILE: conmax.jpg DESCRIPTION: Example SoC with the CONMAX IP Core
Status
- October 2002, Maintenance update: Fixed a typo in parameter passing and in the specification
- May 2002. Several users of the core have reported that the core performs as specified. Project is now considered completed.
- 10/19/2001 Initial Release.
- I will post a message to cores@opencores.org each time I have an update
Change log
- 10/19/2001 Initial Reslease
This IP Core is provided by:
www.ASICS.ws - Solutions for your ASIC/FPGA needs -
