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Details
Category: System on Chip
Created: Nov 26, 2016
Updated: Jan 27, 2020
Language: Verilog
Other project properties
Development Status: Alpha
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
Is a Open 8051 based Embededed System, Include a 8051 with Following SubSystem
- 32K Program Memory
- 32K Data Memory
- 1x I2C Master
- 1x I2C Slave
- 1x SPI Master
- 1x Uart
