ECO32 32-bit RISC Microprocessor SoC

ECO32 32-bit RISC Microprocessor SoC

Details

Category: System on Chip

Created: February 03, 2014

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Alpha

Additional info: FPGA proven

WishBone compliant: No

WishBone version: n/a

License: BSD

Description

The ECO32 system is a microprocessor system-on-chip, consisting of
a 32-bit CPU and several controllers for peripheral devices (keyboard,
character display, timer, serial line, SDRAM, Flash-ROM, IDE disk).

The ECO32 CPU is a simple 32-bit RISC processor with an instruction
set loosely modelled after MIPS, currently without floating point
instructions. We want to execute some flavour of UNIX on it, so it
has got two operating modes (kernel/user) and a memory management
unit (paging with TLB support). The processor was first simulated
at the instruction set level (the simulator is included), then at
the HDL level, and has finally been implemented in an FPGA.

Included in the project is an ANSI C compiler (LCC from Fraser and
Hanson) with a back-end for ECO32, a simple tool chain (assembler
and linker), as well as a monitor program, which can be flashed into
non-volatile memory on an FPGA board. Also included are tools to
create a disk image which can be used as the system disk with the
simulator. A disk server makes this "disk" available for the real
ECO32 on an FPGA over a serial line. An IDE (parallel ATA) disk or
an SSD can be accessed from the real ECO32 as well.