AHB to Wishbone Protocol Bridge
Details
Category: System on Chip
Created: July 31, 2007
Updated: January 27, 2020
Language: Verilog
Other project properties
Additional info: Design done, FPGA proven, Specification done
WishBone compliant: Yes
WishBone version: n/a
License: n/a
Description
AHB Protocol to Wishbone Protocol Bridge.
Features
- AHB 2.0 compliant
- Wishbone B.3 compliant
- AHB Burst NOT SUPPORTED
- Fully synthesisable
- Synchronous
- Verilog RTL
- Includes a Verilog Testbench with 10 Testcases
Status
- RTL : Complete
- Testbench : Complete
- Document : Complete
