PSS (Programmable Supervisor For Systems-on-Chip)

PSS (Programmable Supervisor For Systems-on-Chip)


Category: System on Chip

Created: April 17, 2016

Updated: January 27, 2020

Language: Verilog & VHDL

Other project properties

Development Status: Alpha

Additional info: FPGA proven

WishBone compliant: No

WishBone version: n/a

License: BSD


PSS (Programmable Supervisor for Systems-on-chip) is a soft IP core that targets to provide the basic means for conducting service operations independently from the main processing logic within system-on-chip (SoC) design. The system offers data exchange capabilities, directed via UART interface (host interface), optional central processing unit and a set of tcl commands to control the system from the host computer.
The motivation for the project is to provide simple, but yet functional starting point in system-on-chip or system-on-FPGA design with data transfer and onboard processing capabilities, but when the solution should not be resource-hungry to make design cycles as short as possible (primarily if you use FPGA) or leave maximum resources for custom data processing units. On modern machines, PSS alone typically takes minutes to progress through the whole compilation flow. PSS can be utilized for system initialization, debug, or programmed (either statically or dynamically) to support complex host interface transactions, that may include integrity verification, decompression, etc. Besides being used as a core unit of an initial SoC design prototype or a controller for accelerator-intensive designs, it can be used as auxiliary monitoring and debug processor in addition to the main and more powerful application processor.
Current implementation of PSS uses FreeBSD-licensed ZPU core as a central processing unit. PSS itself is licensed under FreeBSD as well.