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Category: Communication Controller IP Cores (195)

Core1990 : Royalty-free Interlaken Protocol

Core1990 is a point-to-point communication protocol using the royalty-free Interlaken protocol as its foundation. It is designed by engineers and…

License : LGPL
Language : VHDL

1Gbit Ethernet UDP IP Stack

Implements UDP, IPv4, ARP protocols Zero latency between UDP and MAC layer (combinatorial transfer during user data phase) Allows full control of…

License : BSD
Language : VHDL

SpaceWire SystemC

If you liked our work is want to help contribute to the future progress of others who have seen help us by donating. ###…

License : Others
Language : Other

Open-source FPGA Communication Framework

FPGA-CF is an open-source, portable, extensible communications package that consists of a small hardware core (less than 600 slices) and and a…

License : BSD
Language : Verilog & VHDL

IEEE 802.3-2008 Clause 36 PCS 1000BASE-X

Verilog implementation of IEEE 802.3-2008 Clause 36 - Physical Coding Sublayer (PCS) type 1000BASE-X (1000baseLX and/or 1000baseSX)

License : LGPL
Language : Verilog

10/100M Ethernet-FIFO Convertor

n/a

License : LGPL
Language : Verilog

10/100/1000 Mbps tri-mode Ethernet MAC Controller

mail group is added to track all the Q&A from the author. If you have any question about the design, please send your question to mail group.…

License : LGPL
Language : Verilog

100 Mbps Ethernet MAC Layer Switch

Ethernet MAC Layer Switch. The switch receive 100 MB/s data rate from 6 channels and direct each frame received to its destination port. The switch…

License : LGPL
Language : Verilog

10G Ethernet MAC Core with IEEE 802.3ae Compliant

The 10G ethernet mac core. It is compliant with ieee 802.3ae. Our plan is: 1. reading specification 2. observation of different companies 10g…

Language : Verilog

E1-G.703,G.704,G.706 Framer/deframer

Features - feature1 - feature2 Status Ready for downloading via CVS. Path: e1framer

Ethernet 100/1000 Mbps

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License : LGPL
Language : VHDL

General-Purpose I/O (GPIO) Core

The GPIO IP core is user-programmable general-purpose I/O controller. Its use is to implement functions that are not implemented with the dedicated…

Ethernet 10GE MAC

The 10GE MAC Core implements the Media Access Control functions for 10Gbps operation as defined in IEEE Std 802.3ae. Features 1. Interfaces - XGMII…

License : LGPL
Language : Verilog

Minimal UART Core

This is another UART project, but is different because that it is very small and will occupy less macrocells on a CPLD. The purpose of this core is…

License : LGPL
Language : VHDL

Lzs

Please download source code from: https://github.com/linuxbestlzs

License : LGPL
Language : Verilog & VHDL

SPORT Interface

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License : LGPL
Language : Verilog

UDP/IP Core

VHDL implementation of a UDP/IP core! Area-optimized for direct PC-FPGA communication! An advanced/versatile version of the core is included in the…

License : GPL
Language : VHDL

USB To UART

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License : LGPL
Language : Verilog

1G Ethernet DPI in Verilog

Current project provides idea of complex network design verification via [{Linux-tunnel interface} + SystemVerilog DPI-C}].

License : LGPL
Language : Verilog

1G Ethernet ARP Communication Controller FPGA

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License : LGPL
Language : VHDL