Minimal UART Core

Minimal UART Core


Category: Communication Controller

Created: March 07, 2009

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Planning

WishBone compliant: No

WishBone version: n/a

License: LGPL


This is another UART project, but is different because that it is very small and will occupy less macrocells on a CPLD.

The purpose of this core is only to implement a very basic UART, without handshaking or FIFO's.

It was developed to be syntezizable on a large number of syntesis tools, so it can be adapted to your device easily.

On the first implementation was used a Xilinx Spartan 3E, with 64 occupied slices.

Please read the documentation, it have useful implementation examples.

For the testing was used the Modelsim simulator and a Enterpoint Drigmorn board, connected with some hardware, as described on the documentation.

If this core was useful I will be very pleased if you send me some information of your project.

For bugs send me an email, as soon as possible the corrections will be done.


Can work on a small CPLD.
Works with CPU's using interruptions.
Can be even smaller changing constants and generics


- Post rout tested on modelsim simulator
- Tested on xilinx ISE simulator
- Implemented on seven segment display
- Implemented on KS0070B display, see documentation for details