1G Ethernet DPI in Verilog

1G Ethernet DPI in Verilog

Details

Category: Communication Controller

Created: October 08, 2016

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Stable

Additional info: Design done, FPGA proven

WishBone compliant: No

WishBone version: n/a

License: LGPL

Description

Current project provides idea of complex network design verification via [{Linux-tunnel interface} + SystemVerilog DPI-C}].