ISO7816 3 Master on FPGA
Details
Category: Communication Controller
Created: January 09, 2011
Updated: January 27, 2020
Language: Verilog
Other project properties
Development Status: Alpha
Additional info: FPGA proven
WishBone compliant: No
WishBone version: n/a
License: BSD
Description
This project aims at implementing a basic iso7816:3 master which can be controlled by software or by a state machine.
This is a work in progress. Currently, a draft implementation is being crafted just to identify the design challenges.
Once it is completed, the plan is to make a precise spec of a final version and then implement it.
Currently the IP supports only T=0, in direct and inverse convention. It does not handle T=0 parity error signaling / retry mechanism yet.
FPGA test included only the UART, not the master module.
