Ethernet 10GE MAC

Ethernet 10GE MAC


Category: Communication Controller

Created: May 19, 2008

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Stable

Additional info: Design done, FPGA proven, Specification done

WishBone compliant: Yes

WishBone version: n/a

License: LGPL


The 10GE MAC Core implements the Media Access Control functions for 10Gbps operation as defined in IEEE Std 802.3ae.


1. Interfaces
- XGMII Interface (64-bit single clock edge)
- POS-L3 like Interface for core logic side
- Wishbone Interface for control
2. Inter-Frame GAP
- Deficit Idle Count per Clause 46
3. Pause Frames
- Received Pause Frames filtering
- Receive Indication
4. LAN mode operation
5. Link Status
- Local Fault Detection
- Remote Fault Detection/Indication
6. Latency
- Low-latency flow-through mode (120ns TX, 160ns RX)

Release Notes

1. Some issues reported with synthesis of FIFO's in Xilinx. Recommend using XIL define.


- (05/31/2008) Verilog code completed
- (06/06/2008) SystemC and Verilog simulations completed
- (03/06/2009) Validated in Altera FPGA running traffic against other MAC
- (03/06/2009) Validated interfacing to external 10GE PHY using XAUI links
- (12/13/2009) Changed packet interface to big endian
- (12/13/2009) Added SERDES examples to tb_xge_mac.v
- (2/7/2012) Updates for Xilinx synthesis
- (2/15/2012) Core user reported passing traffic in Xilinx FPGA
- (11/23/2012) Design improvements for timing
- (11/23/2012) Added XIL define option for FIFO synthesis with Xilinx
- (11/23/2012) Added a prototype System Verilog testbench (not for general use)
- (11/25/2012) Added basic packet statistics. Timing improvements. Reduced FIFO size.

Future Developments

- RMON Statistics
- Store-and-forward mode