UDP/IP Core
Details
Category: Communication Controller
Created: February 09, 2010
Updated: January 27, 2020
Language: VHDL
Other project properties
Development Status: Stable
WishBone compliant: No
WishBone version: n/a
License: GPL
Description
VHDL implementation of a UDP/IP core! Area-optimized for direct PC-FPGA communication!
An advanced/versatile version of the core is included in the PC-FPGA Communication Platform project!
