1Gbit Ethernet UDP IP Stack

1Gbit Ethernet UDP IP Stack


Category: Communication Controller

Created: October 11, 2011

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Stable

Additional info: Design done, FPGA proven

WishBone compliant: No

WishBone version: n/a

License: BSD


Implements UDP, IPv4, ARP protocols
Zero latency between UDP and MAC layer (combinatorial transfer during user data phase)
Allows full control of UDP src & dst ports on TX.
Provides access to UDP src & dst ports on RX (user filtering)
Couples directly to Xilinx Tri-Mode eth Mac via AXI interface
choice of ARPV2 layer with multislot cache, or smaller single slot ARP for point to point implementations
Separate building blocks to create custom stacks
Easy to tap into the IP layer directly
Separate clock domains for tx & rx paths
Tested for 1Gbit Ethernet, but applicable to 100M and 10M
More detail in doco under Downloads
- provided by Peter Fall and the FIXQRL project
- Applicable license is the "BSD 3-Clause License"