Synthesizable USB 1.1 Compliant Function Core

Synthesizable USB 1.1 Compliant Function Core


Category: Communication Controller

Created: September 19, 2002

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Stable

Additional info: FPGA proven

WishBone compliant: No

WishBone version: n/a

License: n/a


USB 1.1 slave/device IP core. Default configuration is 6 endpoints:
1 Control, 1 Isochronous IN, 1, Isochronous Out, 1 Bulk IN, 1 Bulk
Out, 1 Interrupt IN. Includes control engine, providing full enumeration
process in hardware - no external micro-controller necessary.
Derived from my USB 2.0 Function IP core, except all the high speed
support logic has been ripped out and the interface was changed from
shared memory to FIFO based.

A basic test bench is now included as well. It should be viewed
as a starting point to write a more comprehensive and complete
test bench.

I expect the users of this core to have some fundamental USB knowledge
and be familiar with the UTMI specification and with the general USB
transceivers (e.g. from philips). If you are not familiar with these two
you should check out and read up on this subject ...


- USB 1.1 Compliant Function
- Hardware enumeration support
- No micro controller/CPU required
- FIFO based interface
- Written In Verilog
- Fully Synthesisable
- Tested in Hardware


This core is fully functional and completed.
It was verified in hardware in an XESS XCV800 FPGA prototype board.
- Sept. 25 2002
- Added a basic test bench
- Changed Top Level


To use this IP core, you must also download the USB 1.1 PHY , Generic FIFOs and the Generic memories models.

This IP Core is provided by: - Solutions for your ASIC/FPGA needs -