RS232 with Buffer State and Wishbone Interface

This is a small UART to byte uPC interface (compliant with RS232 and RS3232 CI's).
Ideal to use with soft/hard processors in a FPGA project.

Designed to sync internal clock of RX path. Independent clock sources (TX/RX).

uPC Interface

TX:
- TX data;
- TX request;
- TX end of send;

RX:
- RX data;
- RX data ready (data valid);