SSP_Slv - A Slave Interface for SSP

SSP_Slv - A Slave Interface for SSP


Category: Communication Controller

Created: November 01, 2013

Updated: January 27, 2020

Language: Verilog

Other project properties

Additional info: Design done, FPGA proven

WishBone compliant: No

WishBone version: n/a

License: LGPL


This project provides a slave interface for a Synchronous Serial Peripheral (SSP) as found on NXP LPC21xx microprocessors. The implementation provided here supports a 16-bit frame size. Of the 16 bits defined in the serial interface, the first three bits function as a register address, the fourth bit is a read/write control bit, and the remaining 12 bits function as read/write data.

This format is used in several commercial products to interface a LPC2138/LPC2148, or other processor equipped with an SSP or SPI master interface, to an FPGA. It enables the expansion of the LPC2138/LPC2148 with custom interfaces hosted in a variety of FPGAs. Within the FPGA, a parallel is formed using the register address, read/write control signal, and the data signals.

The master transmits a synchronous serial frame to this SSP_Slv module (MSB first). It returns the first four bits to the master, and creates a read/write pulse to the slave logic during the last rising edge of the 16-bit frame. It also samples the addressed register on the fourth clock of the frame. It generates a read pulse to the internal logic after capturing the data from the addressed register. This read pulse can be used to advance FIFOs, etc.

The interface logic is driven from the SSP/SPI SCK, and the slave select signal resets the interface state machine. Asserting slave select releases the reset signal of the module, and de-asserting slave select asserts the module's reset signal. Because the SSP_Slv is clocked by SCK, clock domain crossing logic and synchronizing registers are used where necessary to simplify connecting to peripherals operating on another clock domain.


Found an issue with the use of MSB (bit 15, RA[2]) during the first SSP transfer cycle. The register's previous asynchronous reset signal, SSP_Rst, was extended by a bit period and therefore prevented the register from being loaded from MOSI on the rising edge of SCK. Changed the register's reset signal to Rst_SSP, the module's reset signal, which is deasserted on the assertion of SSEL. This corrects change the issue.

Synthesis/PAR Results

The following tables define the synthesis and PAR results for the SSP slave module. It is not intended to be used as a stand-alone implementation, but as an interface for serial peripherals in an FPGA.




Module Partition Slices Slice Reg LUTs LUTRAM BRAM MULT18X18 BUFG DCM
[-] SSP_Slv   52/52 54/54 31/31 0/0 0/0 0/0 1/1 0/0






Met Constraint Check Worst Case Slack Best Case Achievable Timing Errors Timing Score
Yes Autotimespec constraint for clock net SCK_BUFGP SETUP/HOLD N/A ns/1.035ns 4.413ns 0/0 0/0





, Synthesis/PAR Results - XC3S50A-4VQ100I FPGA


Attribute Used Avail %
Number of Slice Flip Flops 54 1408 3%
Number of 4 input LUTs 31 1408 2%
Number of occupied Slices 52 704 7%
Number of Slices related logic 52 52 100%
Number of Slices unrelated logic 0 52 0%
Total Number of 4 input LUTs 31 1408 2%
Number used as logic 31    
Number used as a route-thru 0    
Number used as Shift registers 0    
Number of bonded IOBs      
Number of bonded pads 39 68 57%
IOB Flip Flops N/A    
Number of BUFGMUXs 1 24 4%
Number of DCMs 0 2 0%
Number of RAMB16BWEs 0 3 0%