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Category: DSP Core IP Cores (41)

LinkRunCCA : Linked List & Run-length-based Techniques

LinkRunCCA is a real-time single-pass connected component analysis/ connected component labeling (CCA/CCL) implemented in Verilog HDL. It can be…

License : LGPL
Language : Verilog

Canny Edge Detector with 9x9 Mask

Canny edge detector with a 9x9 mask (gradient + gaussian filtering with sigma = sqrt(2)). Able to produce a throughput of 1 pixel per clock cycle.…

License : LGPL
Language : VHDL

Adaptive LMS equalizer

n/a

License : GPL
Language : VHDL

Wishbone DSP Compatible Cores

WDSP project includes three System on Chip (SoC) cores, which implement the Digital Signal Processing (DSP) functions: Finite Impulse Response…

License : LGPL
Language : VHDL

All-pole Lowpass IIR Filters

The circuits found here implement digital leapfrog filters as described in <http://en.wikibooks.org/wiki/Signal_ProcessingDigital_Filters>.…

License : LGPL
Language : VHDL

Biquad IIR Filter Core

The difference equation for the biquad filter is: y[n] = b10*x[n] + b11*x[n-1] + b12*x[n-2] + a11*y[n-1] + a12*y[n-2] This equation is implemented…

Lossless CF FIR Filter

Cores are generated from Confluence; a modern logic design language. Confluence is a simple, yet highly expressive language that compiles into…

Fixed-Point Cascaded FIR Filter

FIR filter - architecture written with pure verilog - parameterizable in verilog code - cascaded - processing is paralleled - data and coefficients…

License : LGPL
Language : Verilog

Cascaded Integrator Comb - CIC Decimation Filter

This is a structural model for cascaded integrator comb (CIC) decimation filters. The filter consists of integrator, downsampler and comb stages.…

License : GPL
Language : SystemC

Hogenauer Pruning CIC Filter

n/a

License : LGPL
Language : Verilog

Cascaded Integrator-comb (CIC) Digital Filter Core

Cascaded integrator-comb (CIC) digital filters are computationally efficient implementations of narrowband lowpass filters and are often embedded…

License : LGPL
Language : Other

Generic FIR Digital Filters

This is an elementary generic structural VHDL code for FIR digital filters in transposed-form and direct-form implementations. This project covers…

License : GPL
Language : VHDL

Fully Pipelined DDS Synthesizer or NCO

The DDS IP core (dds_synthesizer) is a implementation of a direct digital frequency synthesizer (DDS) (also called number controlled oscillator,…

License : LGPL
Language : VHDL

Configurable High Speed Viterbi Decoder in Verilog

n/a

License : GPL
Language : Verilog

Double Clocked FFT Core

The goal of this project is to create an IP core for an FFT that runs, in a pipelined fashion, at two samples per clock. A C++ program will…

License : GPL
Language : Verilog

FIRGEN/MULTGEN - VHDL Core Generator

VHDL core generator FIRGEN Project generates optimized VHDL codes for FIR Filters and Multiplier arrays using "Nonrecursive Signed Common…

License : GPL
Language : Other

Dynamic Resizable Streaming FFT2

Integer streaming FFT fixed size and resizable. Language - SystemVerilog. Generator of rotation coefficients in MatLab. Includes Quartus project…

License : LGPL
Language : Verilog

VHDL Viterbi Decoder : An AXI4-Stream Compliant

A fully configurable VHDL Viterbi decoder compliant with the AXI4-Stream interface. Most standards using convolutional codes like Wifi or GSM are…

License : GPL
Language : VHDL

8-bit Fast Hadamhard Transform for Xilinx FPGA

The RTL computes Fast Hadamhard Transform of 8-bit input data. The code has been developed using standard FHT algorithm using matrix addition. The…

Language : Verilog

Fast Fourier Transformer (FFT) based FIR Filter

FFT-based FIR Filter is a unit to perform the finite impulse responce filter based on the Fast Fourier Transform (FFT). It performs the convolution…

License : LGPL
Language : VHDL