8-bit Fast Hadamhard Transform for Xilinx FPGA
Details
Category: DSP Core
Created: April 10, 2007
Updated: January 27, 2020
Language: Verilog
Other project properties
Development Status: Beta
Additional info: Design done
WishBone compliant: No
WishBone version: n/a
License: n/a
Description
The RTL computes Fast Hadamhard Transform of 8-bit input data. The code has been developed using standard FHT algorithm using matrix addition. The code has been functionally verified and also synthesized for Xilinx FPGA.
Features
- feature1
- feature1.1
-feature1.2
-feature2
Status
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- status2
