Canny Edge Detector with 9x9 Mask
Details
Category: DSP Core
Created: June 09, 2014
Updated: January 27, 2020
Language: VHDL
Other project properties
Development Status: Beta
Additional info: Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
Canny edge detector with a 9x9 mask (gradient + gaussian filtering with sigma = sqrt(2)). Able to produce a throughput of 1 pixel per clock cycle. Succesfully implemented on a Virtex4 up to 300Mhz clock frequency.
