Fixed-Point Cascaded FIR Filter
Details
Category: DSP Core
Created: May 21, 2015
Updated: January 27, 2020
Language: Verilog
Other project properties
Development Status: Alpha
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
FIR filter
- architecture written with pure verilog
- parameterizable in verilog code
- cascaded - processing is paralleled
- data and coefficients stored in RAM - suitable for long pulse response FIR and limited registers count
- complex data
- fixed point
* load coefficient from input data as option - for echo/sonar/radar/etc processing
FPGA resources using
Altera Cyclone IV E EP4CE22E22C8
Parameters of filter
| Input data width | 14 b, 2 channels |
| Pulse response length | 2048 samples |
| Cell size | 1024 (2 cells for 2048 samples used) |
| Output data width | 28 b, 2 channels |
,
Resources usage
| Total logic elements | 840 |
| - Total combinational functions | 558 |
| - Dedicated logic registers | 537 |
| Total registers | 537 |
| Total memory bits | 114,688 |
| Embedded Multiplier 9-bit elements | 20 |
