Or try an example search: 3DES
Introducing Calibre nmLVS-Recon
Please write a description of the project here. It is used as a MetaTag (search engines looks at this).
Project information The Modular Simultaneous Exponentiation core is a flexible hardware design to support modular simultaneous exponentiations in…
This is a single precision floating point unit. It is fully IEEE 754 compliant. It can currently perform Add/Sub, Mul and Divide operations, as…
AES (Advanced Encryption Standard) is a specification published by the American National Institute of Standards and Technology in 2001, as FIPS…
Simple AES (Rijndael) IP Core. I have tried to balance this implementation and to trade off size and performance. The goal was to be able to fit in…
Here you can find two different implementations of AES encryption algorithm: - A 128 bits AES algorithm focusing on very low area applications. - A…
The NIST has selected cipher Rijndael as AES on October 20, 2000 based on the combination security, performance, efficiency, ease of implementation…
Consecutive AES core Description of project.. Features - AES encoder - 128/192/256 bit - AES decoder - 128/192/256 bit Status - Key Expansion added…
This Core implements the Advanced Encryption Standard (Rijndael Algorithm) according to the NIST standard as documented in FIPS-197. This AES core…
While there are many AES cores around, this one is designed with LUT6 based FPGA architecture in mind from day one. The AES Decryption Core for…
Three different implementations of the AES-128 (VHDL).
The AES behavioral model is not an encryption/decryption core, but a tool to facilitate the verification of AES IPs in HDL simulation.…
Four stage pipeline design working at 361.890MHz on Xilinx's 28nm Kintex 7 speed grade 3 FPGA device. Calculating 4 blocks parallely,…
The AES-128 pipelined cipher module uses AES algorithm which is a symmetric block cipher to encrypt (encipher) information. Encryption converts…
Features - Latency insensitive design - Should be portable to most bus architectures/platforms - Easily amenable to multi-clock domain extension -…
This IP core loads an unsorted, encrypted list of numbers from memory. It then decrypts and sorts the list. Sorting is acheived using a…
General Description I know there are plenty of AES (Rijndael) implementations around. I created my own anyway because I was unhappy with either the…
Bit-serial multiplication on the NIST B-163 curve. This implementation utilizes DSP481E blocks (Artix-7 FPGA).
Don't have an AAC account? Create one now.
Forgot your password? Click here.