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Category: Crypto Core IP Cores (70)

Fast AES-128 Encryption Only Cores

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License : Others
Language : Verilog

HIGHT Crypto Core

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License : LGPL
Language : Verilog

Flexible Design of a Modular Simultaneous Exponentiation Core

n/a

License : LGPL
Language : VHDL

Floating Point Unit - An IEEE 754 Compliant

This is a single precision floating point unit. It is fully IEEE 754 compliant. It can currently perform Add/Sub, Mul and Divide operations, as…

Language : Verilog

Three Cores AES Encryption Algorithm

AES (Advanced Encryption Standard) is a specification published by the American National Institute of Standards and Technology in 2001, as FIPS…

License : Others
Language : Verilog

Simple AES (Rijndael) on Xilinx Spartan Series

Simple AES (Rijndael) IP Core. I have tried to balance this implementation and to trade off size and performance. The goal was to be able to fit in…

Language : Verilog

AES Encryption Algorithm 128/192 Bits

Here you can find two different implementations of AES encryption algorithm: - A 128 bits AES algorithm focusing on very low area applications. - A…

Language : Verilog

NIST AES - Rijndael Algorithm

The NIST has selected cipher Rijndael as AES on October 20, 2000 based on the combination security, performance, efficiency, ease of implementation…

AES Encoder and Decoder Modules

n/a

Language : VHDL

AES 128 Advanced Encryption Standard Algorithm

This Core implements the Advanced Encryption Standard (Rijndael Algorithm) according to the NIST standard as documented in FIPS-197. This AES core…

License : LGPL
Language : VHDL

AES Decryption Core for FPGA Implementations

While there are many AES cores around, this one is designed with LUT6 based FPGA architecture in mind from day one. The AES Decryption Core for…

License : LGPL
Language : Verilog

AES 128 Three Implementations in VHDL

Three different implementations of the AES-128 (VHDL).

License : GPL
Language : VHDL

AES SystemVerilog Behavioral Model

The AES behavioral model is not an encryption/decryption core, but a tool to facilitate the verification of AES IPs in HDL simulation.…

License : LGPL
Language : Verilog

128-bit AES Decryption Core

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License : LGPL
Language : VHDL

AES Encryption All Keylength

Four stage pipeline design working at 361.890MHz on Xilinx's 28nm Kintex 7 speed grade 3 FPGA device. Calculating 4 blocks parallely,…

License : BSD
Language : VHDL

Pipelined AES 128 Encryption Module

The AES-128 pipelined cipher module uses AES algorithm which is a symmetric block cipher to encrypt (encipher) information. Encryption converts…

License : LGPL
Language : Verilog

Configurable Bluespec MD6-512

n/a

Language : Other

Pipelined AES Bluespec Cryptosorter

This IP core loads an unsorted, encrypted list of numbers from memory. It then decrypts and sorts the list. Sorting is acheived using a…

Language : Other

Avalon AES ECB Core (128, 192, 256 Bit)

n/a

License : BSD
Language : VHDL

B-163 EC Arithmetic

Bit-serial multiplication on the NIST B-163 curve. This implementation utilizes DSP481E blocks (Artix-7 FPGA).

License : GPL
Language : VHDL