AES Encryption Algorithm 128/192 Bits
Category: Crypto Core
Created: July 02, 2004
Updated: January 27, 2020
Other project properties
Development Status: Stable
Additional info: FPGA proven
WishBone compliant: Yes
WishBone version: n/a
Here you can find two different implementations of AES encryption algorithm:
- A 128 bits AES algorithm focusing on very low area applications.
- A 192 bits AES algorithm focusing on very low area applications.
The 128 bits low area implementation takes about 500 cycles to encrypt/decrypt a block.
The 192 bits low area implementation takes about 280 cycles to encrypt/decrypt a block.
They don't use memories to store the S-box and have many other architectural improvements to reduce the area comsumption.
Implements the encoder and decoder in the same block.
The cores were written in SystemC RTL, and verified using TLM(Transaction Level Modelling Style).
Verilog synthesizable code is also provided
All implementations have been tested on a Xilinx Virtex2 FPGA succesfully.