Pipelined AES 128 Encryption Module

Pipelined AES 128 Encryption Module


Category: Crypto Core

Created: September 06, 2013

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Stable

Additional info: Design done, FPGA proven, Specification done

WishBone compliant: No

WishBone version: n/a

License: LGPL


The AES-128 pipelined cipher module uses AES algorithm which is a symmetric block cipher to encrypt (encipher) information. Encryption converts data to an unintelligible form called ciphertext .Here the AES algorithm is capable of using cryptographic keys of 128bit to do this conversion .This module is optimized for speed as it pipeline hardware to perform repeated sequence called round. This module synthesized on Xilinx virtex 6 6vcx240tff784-2 board using ISE. Fuctional and gate level simulation were done using AES validation suite (AESVS) vectors


-128 bit data
-128 bit Cipher Key
-One Clock domain
-Optimized for speed
-Pipelined architecture
-Generic RTL (vendor independent)