Pipelined Architecture of AES 128 Bit

Pipelined Architecture of AES 128 Bit


Category: Crypto Core

Created: March 22, 2010

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Stable

Additional info: Design done

WishBone compliant: No

WishBone version: n/a

License: LGPL


This is a fully pipelined implementation of the AES (rijndael) cipher with 128 bit keysize. Post place and route logs show the maximum speed to be 333 MHz when implemented on a Virtex-5 LX50T speed grade -1 FPGA with 45% LUT utilization and 27% register utilization. This comes out to a maximum throughput of ~ 42Gbps with an average of 1 encryption every cycle. The overall design has a latency of 30 clock cycles. A brief documentation is available here.

P.S. If you download the project and find it to be useful, please do drop me a mail at my address subhasis256@opencores.org. I will appreciate it very much. 😊



  • Design a corresponding fully pipelined decryption engine