Configurable Bluespec MD6-512

Configurable Bluespec MD6-512


Category: Crypto Core

Created: August 06, 2008

Updated: January 27, 2020

Language: Other

Other project properties

Development Status: Beta

Additional info: FPGA proven

WishBone compliant: No

WishBone version: n/a

License: n/a



- Latency insensitive design
- Should be portable to most bus architectures/platforms
- Easily amenable to multi-clock domain extension
- Support for long burst transfers
- Configurable number of compression cores, compression core parallelism


This project is under on-going development as we seek to explore and to improve the architecture of the implementation.

We have demonstrated this architecture on the Xilink XUP board, on which we have obtained throughputs in excess of 233 MB/s for MD6-512