Pipelined AES Bluespec Cryptosorter

Pipelined AES Bluespec Cryptosorter

Details

Category: Crypto Core

Created: June 28, 2008

Updated: January 27, 2020

Language: Other

Other project properties

Development Status: Beta

Additional info: FPGA proven

WishBone compliant: No

WishBone version: n/a

License: n/a

Description

This IP core loads an unsorted, encrypted list of numbers from memory. It then decrypts and sorts the list.

Sorting is acheived using a high-throughput, heavily parametric mergesort core.

 

Features

- Highly parametric mergsort core
- folds a single comparator across multiple fifos mapped onto SRAMs
- compartor scheduler as a parameter
- High speed PLB master core
- achieves effective memory throughput of more than 400MB/s
- uses configurable burst transfers to obtain high throughput
- Pipelined AES core

Status

This project is completed and development is closed. It has been successfully implemented on FPGA.