AES SystemVerilog Behavioral Model

AES SystemVerilog Behavioral Model


Category: Crypto Core

Created: July 03, 2013

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Beta

Additional info: Design done, Specification done

WishBone compliant: No

WishBone version: n/a

License: LGPL


The AES behavioral model is not an encryption/decryption core, but a tool to facilitate the verification of AES IPs in HDL simulation.

Traditionally crypto IPs are verified with C/C++ model, but that requires you to either interface with an external language in your HDL testbench, or to modify your C/C++ model to export test vectors in a format acceptable by your testbench. Either way is time consuming. A native SystemVerilog model elimates the need to interface with an external language model. You can include this model in your testbench and drive it in your simulation like a C model.

Both encryption and decryption are now supported.

The model itself is an un-timed SystemVerilog class which implements the encryption and decryption algorithm described in the FIPS-197 specification. A set of tasks (methods) is provided for users to drive the model to go through the encryption and decryption algorithm to generate known good results (either per round intermediate results or final plaintext/ciphertext). It can be included in a testbench as golden model or test vector generator.