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Category: Processor IP Cores (191)

OpenRISC 1000 Architecture 32/64-bit RISC/DSP

Introduction The aim of the OpenRISC project is to create a free, open source computing platform available under the GNU (L)GPL license. Platform…

License : LGPL
Language : Verilog

AltOr32 - Alternative Lightweight OpenRisc CPU

AltOR32 is an OpenRISC 1000 architecture derived RISC CPU targeted at small FPGAs and contains only the most basic ISA features from the OpenRisc…

License : LGPL
Language : Verilog

32-bit FORTH processor with Java compiler on Xilinx

A 32-bit FORTH processor conforming to the DPANS'94. This processor was developed as diploma thesis to obtain the academic degree…

License : LGPL
Language : VHDL

8080 Compatible 8-bit CPU

This is an 8080 core I created as a project to get to know Verilog. The 8080 was the second in the series 8008->8080->Z80. It was the second…

Language : Verilog

16-bit Classical CPU Based Loosely on Caxton Foster’s Blue CPU

A 16-bit classical CPU based loosely on Caxton Foster's Blue CPU from the book "Computer Architecture". Includes a cross assembler…

License : LGPL
Language : Verilog

16 Bit Microcontroller VHDL Assembler

Features 800 Xilinx slices for CPU 1000 Xililinx slices for complete SoC Optimized for exeution of C programs VHDL, Assembler, C Compiler,…

License : LGPL
Language : VHDL

16-bit Open uRISC Core Processor

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License : LGPL
Language : VHDL

1664 Microprocessor - Simulator Source Configurable

Overview 16,32,64 bit microprocessor - simulator source configurable. 16 bit fixed instruction length. All instructions conditional. up-to 128…

License : Others
Language : C/C++

Simple RISC 32-bit Pipelined Processor

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License : LGPL
Language : Verilog

MC6809/HD6309 Compatible Core Processor

A verilog, vendor independent, no cycle accurate MC6809/HD6309 compatible processor core. Goals: - Execute all implemented opcodes - Allow…

License : LGPL
Language : Verilog

FPGA-Based 6502 Processor in VHDL

Features - feature1 - feature2 Status - ... - ...

A-Z80 CPU - Implementation of the Venerable Zilog Z80 Processor

Update: Rewritten in pure Verilog, the CPU can now be used on both Altera and Xilinx devices! A-Z80 is a conceptual implementation of the venerable…

License : LGPL
Language : Verilog

Cpu Generator - Cpugen (TM) Generates Customizable RISC CPU Cores

Cpugen (TM) generates customizable RISC cpu cores. It allows direct customization of address/data/instruction bus size, interrupt handling,…

Language : VHDL

i650 - Verilog RTL Implementation of the Venerable IBM 650 Computer

A Verilog RTL implementation of the venerable IBM 650 computer. The goal of this project is to use available source materials to recreate a 650 as…

License : LGPL
Language : Verilog

68hc05 - a MC68HC05 Clone in VHDL as Single File

MC68HC05 A MC68HC05 clone in VHDL as single file. Twice performance as the original. Multiplication is done in one clock cycle. 2007.02.11 first…

Language : VHDL

Synthesizable VHDL 8-bit Microcontroller with Extended Peripheral Set

The goal of this project is to create a very well documented, fully synthesizable VHDL model of an 8-bit microcontroller with extended peripheral…

License : LGPL
Language : VHDL

8-bit Pipelined Processor

n/a

License : LGPL
Language : C/C++

8-bit uP - 8-bit Microprocessor with 5 Instructions

This is 8-bit microprocessor with 5 instructions. It is based on 8080 architecture. This architecture called SAP for Simple-As-Possible computer.…

License : GPL
Language : VHDL

8-bit CPU Optimized for Control Applications 8051 Core

The 8051 microcontroller is member of MCS-51 family, originally designed in the 1980's by Intel. The 8051 has gained great popularity since its…

ASPIDA sync/async DLX Fully-asynchronous Core

The ASPIDA project has implemented an asynchronous IP of the DLX Instruction Set Architecture (ISA) with incorporated support for ISA conversion so…