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Category: Testing / Verification IP Cores (31)

PRBS Signal Generator And Checker

n/a

License : LGPL
Language : Verilog

SystemVerilog Directed Test Bench

The SystemVerilog Directed Test Bench. This project contains an exact duplication of the VHDL Test Bench Package parser and usage model. This…

License : Others
Language : Other

VHDL Whisbone Test Bench

For the development of IP cores a test bench is needed. The given project provides a test bench written in VHDL which controls the stimulus,the…

License : LGPL
Wishbone Version : B.3
Language : VHDL

SoC Generator Using Verilog

n/a

License : LGPL
Language : Verilog

EziDebug - Easy-to-use Versatile Logic Simulation Tool

EziDebug is an easy-to-use versatile logic simulation tool for verification and debugging of digital circuits. It supports inserting scan chains in…

License : LGPL
Language : C/C++

PlTbUtils for Automatic, Self-checking Simulation Testbenches

PlTbUtils makes it easy to create automatic, self-checking simulation testbenches, and to locate bugs during a simulation. It is a collection of…

License : LGPL
Language : VHDL

Boost Converter in Verilog

Please write a description of the project here. It is used as a MetaTag (search engines looks at this).

License : LGPL
Language : Verilog

CPU-to-FPGA Bus Transaction Monitor with JTAG

A CPU-to-FPGA bus transaction monitor, captures the CPU write/read address/data to/from memory-mapped registers that resides in the FPGA, and…

License : LGPL
Language : Verilog

DS1621 Verilog Model with Testing Tasks

DS1621 verilog model with testing tasks. Testing elements assume the existence of the low level write/read (need to be written by the user) and…

License : LGPL
Language : Verilog

Field-Programmable Oscilloscope (FPO) Logic Analyzer

This is FPgaOscilloscope or Field-Programmable Oscilloscope FPO resides in FPGA along with the main project and allow to observe their signals.…

License : GPL
Language : VHDL

FROM and TO VHDL files

For make stimulus of testbench some times need work with files from VHDL. I think that will be very good if some different stimulus will be in one…

License : LGPL
Language : VHDL

c - VHDL Co-Simulation with FLI for Simulator Control

Using ModelSim Foreign Language Interface for c - VHDL Co-Simulation and for Simulator Control on Linux x86 Platform Writing testbenches in VHDL…

License : Others
Language : VHDL

Generic AHB Master Stub for 32/64 data bits, AHB Bursts and Random Wait-states

Generic AHB master stub. Built out of an AXI master and an AXI2AHB bridge. Supports 32/64 data bits, AHB bursts and random wait-states. The design…

License : LGPL
Language : Verilog

Generic AHB Slave Stub for 32/64 data bits, AHB Bursts and Random Wait-states

Generic AHB slave stub. Supports 32/64 data bits, AHB bursts and random wait-states. The design is built according to input parameters: address…

License : LGPL
Language : Verilog

Generic APB Master Stub for APB and APB3 Protocols

Generic APB master stub. Based on an AXI master stub and an AXI2APB bridge. Supports both APB and APB3 protocols (APB3 is with pready and pslverr…

License : LGPL
Language : Verilog

Generic AXI Slave Stub for 32/64 data bits, AXI Bursts and Random Wait-states

Generic AXI slave stub. Supports 32/64 data bits, AXI bursts and random wait-states. The design is built according to input parameters: address…

License : LGPL
Language : Verilog

Generic APB Slave Stub for APB and APB3 Protocols

Generic APB slave stub. Support both APB and APB3 protocols (APB3 is with pready and pslverr). Supports slave error, random and fixed wait-states.…

License : LGPL
Language : Verilog

Generic AXI Master Stub for Multiple AXI IDs, 32/64 data bits, AXI bursts and random wait-states

Generic AXI master stub. Supports multiple internal masters (multiple AXI IDs), 32/64 data bits, AXI bursts and random wait-states. The design is…

License : LGPL
Language : Verilog

HASM TestBench Vector Generator for FPGA/CPLD designs verification

n/a

License : LGPL
Language : VHDL

Standalone Minimalist i2clcd IP Core

i2clcd is a minimalist i2clcd IP core that provides the basic framework for the implementation of custom i2clcd devices. The core provides a means…

License : LGPL
Language : Verilog