Generic AXI Slave Stub for 32/64 data bits, AXI Bursts and Random Wait-states

Generic AXI Slave Stub for 32/64 data bits, AXI Bursts and Random Wait-states

Details

Category: Testing / Verification

Created: April 05, 2011

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Alpha

WishBone compliant: No

WishBone version: n/a

License: LGPL

Description

Generic AXI slave stub. Supports 32/64 data bits, AXI bursts and random wait-states. The design is built according to input parameters: address bits, data bits, AXI command depth, etc. The source files are written in RobustVerilog, a free RobustVerilog parser can be downloaded from http://www.provartec.comedatools