High Load Configurable Test Project

High Load Configurable Test Project Click to expand image


Category: Testing / Verification

Created: May 13, 2014

Updated: November 19, 2019

Language: VHDL

Other project properties

Development Status: Stable

WishBone compliant: No

WishBone version: n/a

License: BSD


The project is intended for checking FPGA-based device for high consumption power.
Number of parameter gives possibility to change number of used LC/DFF, DSP, RAM and I/O.
It can operate at 200 MHz in Cyclone 5E FPGA.
1 LC core is about 1500 LUT4/FF (with default parameters)
1 DSP core is 7 DSP 18*18.
Each LC core also demands 4*N RAM blocks (32 bits width).

To maximize power consumption:
1) Find parameters for maximum FPGA resource usage
2) Fed maximum frequency clock to CLK input (directly or via PLL instantiated in top level)
3) Fed random data to inputs (lower ADC bits or data from PRBS generator)
4) Connect maximal outputs count. Be careful: They are switching simultaneously.


Update of 2016-02-04
I found that some compilers have limit to maximal vector size. For example,
Vivado crashes with more than 16k bits. I have reached that limit for Kintex
Ultrascale devices. So you can use LC_RECURSION parameter to build LC components
recursively. It gives possibility to decrease vector size at top level.