Uart2BusTestBench

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Details

Category: Testing / Verification

Created: January 24, 2016

Updated: November 19, 2019

Language: Other

Other project properties

Development Status: Stable

Additional info: ASIC proven, Design done, FPGA proven, Specification done

WishBone compliant: No

WishBone version: n/a

License: LGPL

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Description

Uart2BusTestBench is implemented using Universal Verification Methodology to perform the functional verification to the RTL design released by Moti Litochevski and Steve MULLER (check this link ).

The Main Features :

Additional C++ program is attached to facilitate baud frequency calculations.
Includes UART BFM which in turn act as UART driver and includes all standard routines which makes it possible to bury it into another Testbench (Like UART VIP).
Includes Register-File BFM which act as slave memory and includes all non-standard routines
Support inserting idle time between transactions.

General Test-bench Architecture

Testbench
You can download The Architecture Specifications from here

Environment Configurations

Field	Description	Possible Choices
Active Edge	The active clock edge at which, the data is changed on the UART buses	Positive Edge Negative Edge
First Bit	Represent the sequence through which the byte is serialized	Most Significant bit Least Significant bit
Data Mode	The data representation through the text commands	ASCII Binary
Number of stop bits	The number of stop bits sent after the latest bit of each byte	One Bit Two Bits
Number of bits	The number of bits through each field transfer	7-bit 8-bit
Parity Mode	The used parity type through each byte	Parity off Parity Even Parity Odd
Response Time	Represent the maximum allowable time through which dut should respond to the driven request.	No Limitations