SystemVerilog Directed Test Bench

The SystemVerilog Directed Test Bench.
This project contains an exact duplication of the VHDL Test Bench Package parser and usage model. This enables users to create a simple test environment for verification efforts using SV. This also enables scripts that were used on the VHDL system to be reused in a SV environment. (providing the same functionality is coded in the SV environment.)

Current state is Beta, please report any problems to the bug tracking system so I can address issues.