DS1621 Verilog Model with Testing Tasks

Details
Category: Testing / Verification
Created: December 17, 2009
Updated: January 27, 2020
Language: Verilog
Other project properties
Development Status: Beta
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
DS1621 verilog model with testing tasks. Testing elements assume the existence of the low level write/read (need to be written by the user) and include the macro tasks based on that write/read tasks. A test with macros is included. Only the Slope and the Counter registers are not supported.