EziDebug - Easy-to-use Versatile Logic Simulation Tool

EziDebug - Easy-to-use Versatile Logic Simulation Tool


Category: Testing / Verification

Created: July 26, 2013

Updated: January 27, 2020

Language: C/C++

Other project properties

Development Status: Stable

WishBone compliant: No

WishBone version: n/a

License: LGPL


EziDebug is an easy-to-use versatile logic simulation tool for verification and debugging of digital circuits. It supports inserting scan chains in projects. Furthermore,more functions and characteristics will be opened. This manual is intended for users with no previous experience with EziDebug . It introduces you with the basic flow how to set up EziDebug. The example used in this tutorial is a small design written in Verilog and only the most basic commands will be covered in this manual. This manual was made by using Version 1.0 of EziDebug on Windows.