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Category: ECC Core IP Cores (21)

802.3an LDPC Decoder

LDPC decoder for 10GBase-T Ethernet (802.3an), based on Gallager's A algorithm. See also…

Language : Verilog

Constellation Encoder

Features - feature1 - feature2 Status - ... - ...

Reed Solomon Encoder/Decoder

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License : LGPL
Language : Verilog

10GBase T Ethernet 802.3an LDPC Encoder

LDPC Encoder for 10GBase-T Ethernet (802.3an). See also http://opencores.orgproject,ldpc_decoder_802_3an,overview (802.3an LDPC Decoder). FILE:…

Language : Verilog

CF Low Density Parity Check - LDPC Decoder

Cores are generated from Confluence; a modern logic design language. Confluence is a simple, yet highly expressive language that compiles into…

Configurable BCH Encoder and Decoder for FPGA

The project describes an IPCore in verilog about binary BCH encoder and decoder. BCH is a popular error correcting code used in storage and…

License : LGPL
Language : Verilog

32-bit Configurable Hamming Generator

This C++ program generates VHDL package with hamming encoder and decoder. It also generates a simple testbench that can be used to evaluate the…

License : GPL
Language : VHDL

Double Error Correcting (DEC) BCH Encoder / Decoder

The double error correcting (DEC) BCH encoder / decoder IP cores. Features : – allows to correct up to 2 errors. – supports…

License : LGPL
Language : Verilog

Product Code Iterative Decoder

Product Code Iterative Decoder An iterative decoder for Product Code, this decoder works for two dimensional product code. Status - Synthesized…

License : BSD
Language : VHDL

Hamming (7,4) Encoder Generator

Hamming (7,4) Encoder: This core encodes every 4-bit message into 7-bit codewords in such a way that the decoder can correct any single-bit error.…

Language : Verilog

PCI Express 16 bit Cyclic redundancy Code CRC Verilog File

PCI express CRC verilog code 16 bit data 32 bit CRC Functional Description Designers commonly use Cyclic Redundacy Codes (CRC) as an alternative to…

Language : Verilog

Reed Solomon Decoder (204,188)

• Reed Solomon Decoder (204,188), with T=8. • Input codeword length is 204 bytes and output length is 188 bytes. • Corrects up to 8…

License : GPL
Language : Verilog

Reed Solomon Encoder

Status - RTL done and design verified using testbench. - Will upload soon. - June 27th 2004, updated. Please click on 'Downloads' (top…

Language : Verilog

High Speed Reed Solomon Decoder (31, 19, 6)

Specifications - Hard-decision decoding scheme - Codeword length (n) : 31 symbols - Message length (k) : 19 symbols - Error correction capability…

Language : Verilog

8-bit Wide Reed Solomon Decoder Encoder

This core implements Reed-Solomon decoder for the 8-bit wide symbols. The core is designed to occupy fewer amounts of logic blocks, be fast and…

License : LGPL
Language : VHDL

Reed Solomon 5,3 Encoder-Decoder in GF256

Reed Solomon (5, 3) Encoder-Decoder in GF(256) - Symbol width : 8-bits. - Encodes every 3-byte message into 5-byte codewords. - Capable of…

Language : Verilog

Spread Spectrum modulator and demodulator using BPSK

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License : LGPL
Language : VHDL

DVB-RCS Turbo Decoder on SOVA Algorithm

This project features a double binary, DVB-RCS turbo decoder using the SOVA algorithm. Two models are included: - a MyHDL model, along with a…

License : LGPL
Language : VHDL

Ultimate CRC Generator using XOR-logic

Ultimate CRC is a CRC generator/checker. Using generics the core can be fully customized. It creates a function of the data input and the CRC…

License : GPL
Language : VHDL

Yet Another Hamming Encoder and Decoder

A hamming encoder and decoder with single-error correcting and double-error detecting capability. The message length can be configured through a…

License : LGPL
Language : VHDL