Double Error Correcting (DEC) BCH Encoder / Decoder

Double Error Correcting (DEC) BCH Encoder / Decoder

Details

Category: ECC Core

Created: April 26, 2011

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Beta

WishBone compliant: No

WishBone version: n/a

License: LGPL

Description

The double error correcting (DEC) BCH encoder / decoder IP cores.

Features :
– allows to correct up to 2 errors.
– supports 16/32/64/128 bit memories (typical memory word sizes).
– operates on complete memory words in a single cycle.
– pure combinational logic design.