Reed Solomon 5,3 Encoder-Decoder in GF256

Details
Category: ECC Core
Created: October 19, 2004
Updated: January 27, 2020
Language: Verilog
Other project properties
Development Status: Stable
Additional info: Design done
WishBone compliant: No
WishBone version: n/a
License: n/a
Description
Reed Solomon (5, 3) Encoder-Decoder in GF(256)
- Symbol width : 8-bits.
- Encodes every 3-byte message into 5-byte codewords.
- Capable of correcting any single symbol error (even if all the 8-bits are erronous) in a codeword.
- This core has two operation modes: Encoding and Decoding.
- In both operation modes, the inputs are taken in byte-by-byte at each clock cyle.
- While encoding, message is input at three clock cycles and the next two clock cyles are reserved for the two parity symbols of the codeword.
- While decoding, received vector is taken in at five clock cycles. But the output is first seen at the sixth clock cyle. However, at the sixth clock cycle another received vector can be fed to the decoder.
Features
- 24 bits of information is encoded at every 5 clocks:
- example: Clock Frequency : 50 MHz --> Baud: 240Mbps
- 32 bits of received vector is decoded every 5 clocks:
- example: Clock Frequency : 50 MHz --> Baud: 320Mbps
- Please go to the "downloads" link and have look at the ppt file.
Status
- status1
- status2