Configurable BCH Encoder and Decoder for FPGA

Details
Category: ECC Core
Created: March 28, 2015
Updated: January 27, 2020
Language: Verilog
Other project properties
Development Status: Alpha
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
The project describes an IPCore in verilog about binary BCH encoder and decoder. BCH is a popular error correcting code used in storage and transmission system. It adds some redundancy check data into original data frame, the redundancy data length depends on correcting capacity, and all the calculation proceed in the Galois Field that is suitable for FPGA.