Reed-Solomon Codec Generator

Reed-Solomon Codec Generator Click to expand image


Category: ECC Core

Created: July 21, 2011

Updated: November 19, 2019

Language: Verilog

Other project properties

Development Status: Stable

Additional info: Design done, FPGA proven, Specification done

WishBone compliant: No

WishBone version: n/a

License: LGPL


This tool working on WinXP is used to generate verilog-RTL for Reed-Solomon Codec.
- Selectable Decoder/Encoder/Both
- Symbol width 3,4,5,6,7,8,9,10,11
- Primitive polynomial
- Erasure Enable/Disable
- Configurable Data I/F
- Automatically available testbench
- Distributed under the GPL license

If you need more customize or hi-performance IP, please let us know.