Ultimate CRC Generator using XOR-logic

Ultimate CRC Generator using XOR-logic


Category: ECC Core

Created: May 05, 2005

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Stable

Additional info: ASIC proven, Design done, FPGA proven, Specification done

WishBone compliant: No

WishBone version: n/a

License: GPL


Ultimate CRC is a CRC generator/checker. Using generics the core can be fully customized. It creates a function of the data input and the CRC register using XOR-logic. Although the levels of logic gets very high for wide data inputs, the throughput still benefits from this architecture, as can be seen from the synthesis page.



  • Executes in one clock cycle per data word
  • Any polynomial from 4 to 32 bits
  • Any data width from 1 to 256 bits
  • Any initialization value
  • Synchronous or asynchronous reset


Revision 1.0 released.