Generic AXI Interconnect Fabric

Details

Category: System on Chip

Created: March 23, 2011

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Stable

WishBone compliant: No

WishBone version: n/a

License: LGPL

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Description

Generic AXI interconnect fabric. It is a multi-master, multi-slave non-blocking AXI fabric with round-robin arbitration. Builds Verilog AXI interconnects according to input parameters: master number, slave number, AXI IDs, etc. The source files are written in RobustVerilog, a free RobustVerilog parser can be downloaded from http://www.provartec.comedatools

Generic AXI master stub
http://opencores.orgproject,axi_master

Generic AXI slave stub
http://opencores.orgproject,axi_slave