OpenRISC 1200 SOC on Terasic DE1
Details
Category: System on Chip
Created: March 16, 2009
Updated: January 27, 2020
Language: Verilog
Other project properties
Development Status: Beta
Additional info: FPGA proven
WishBone compliant: Yes
WishBone version: n/a
License: n/a
Description
Overview
This project is an example of using OpenRISC on an Terasic DE1 development board. UBoot has been ported. The old ecos 2.0 has been ported to ecos 3.0. The adv_debug_sys unit was integrated but not tested.
