Martins SoC Instancing, Simulation Toolchain Builder

Martins SoC Instancing, Simulation Toolchain Builder


Category: System on Chip

Created: November 29, 2018

Updated: January 27, 2020

Language: VHDL

Other project properties

Additional info: Design done, FPGA proven

WishBone compliant: Yes

WishBone version: B.3

License: Others


The MaSoCist is an acronym for 'Martins SoC Instancing, Simulation Toolchain'.

It is a VHDL collection and toolchain based on various open source (and some proprietary) utilities to configure, build and maintain system on chip designs with the focus on lean and mean microcontrollers with optimum code density.

It features the following opensource CPU cores by default:
- neo430 (
- ZPU Zealot architecture
- ZPUng proprietary pipelined ZPU variant (VHDL edition only)

It includes a simple wishbone bridge for optional wishbone compliant core adaptation. All hardware definitions are maintained in XML source, which generates C headers, VHDL decoders and documentation in one 'go'.

Basic peripheral cores are included, such as SIC (system interrupt controller), UART, SPI, TIMER, etc.

The project is currently hosted at: