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Details
Category: System on Chip
Created: Apr 13, 2011
Updated: Jan 27, 2020
Language: Verilog
Other project properties
Development Status: Alpha
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
Generic AHB matrix. It is a multi-master, multi-slave non-blocking AHB matrix with round-robin arbitration. Builds Verilog AHB matrices according to input parameters: master number, slave number, data bits, etc. The source files are written in RobustVerilog, a free RobustVerilog parser can be downloaded from http://www.provartec.comedatools
Related projects
Generic AHB master stub
http://opencores.orgproject,ahb_master
Generic AHB slave stub
http://opencores.orgproject,ahb_slave
