Generic AHB Matrix

Generic AHB Matrix


Category: System on Chip

Created: April 13, 2011

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Alpha

WishBone compliant: No

WishBone version: n/a

License: LGPL


Generic AHB matrix. It is a multi-master, multi-slave non-blocking AHB matrix with round-robin arbitration. Builds Verilog AHB matrices according to input parameters: master number, slave number, data bits, etc. The source files are written in RobustVerilog, a free RobustVerilog parser can be downloaded from http://www.provartec.comedatools

Generic AHB master stub

Generic AHB slave stub